From 6a1e5d9eaab726ac9861d5c9bf5c6eb19c5bb1b1 Mon Sep 17 00:00:00 2001 From: Rodrigo Garcia Date: Mon, 3 Apr 2023 10:31:53 -0300 Subject: [PATCH] Fixes APLL/PLL with RTC Frequency log_d() was displaying APLL for any SoC, but S3 and C3 has not such option, causing compilation errors. --- cores/esp32/esp32-hal-cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c index 5ece7fb60ab..925b8d8b5cd 100644 --- a/cores/esp32/esp32-hal-cpu.c +++ b/cores/esp32/esp32-hal-cpu.c @@ -241,7 +241,11 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){ if(apb_change_callbacks){ triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb); } +#ifdef SOC_CLK_APLL_SUPPORTED log_d("%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == RTC_CPU_FREQ_SRC_PLL)?"PLL":((conf.source == RTC_CPU_FREQ_SRC_APLL)?"APLL":((conf.source == RTC_CPU_FREQ_SRC_XTAL)?"XTAL":"8M")), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb); +#else + log_d("%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == RTC_CPU_FREQ_SRC_PLL)?"PLL":((conf.source == RTC_CPU_FREQ_SRC_XTAL)?"XTAL":"17.5M"), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb); +#endif return true; }