xilinx

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Here are 27 public repositories matching this topic...

hdl-util / hdmi

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Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

Updated Feb 3, 2024
SystemVerilog

trivialmips / nontrivial-mips

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NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

Updated Jul 7, 2020
SystemVerilog

tymonx / logic

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

trivialmips / TrivialMIPS

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MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

cpu fpga mips xilinx systemverilog fpga-soc

Updated Apr 29, 2019
SystemVerilog

BrianHGinc / BrianHG-DDR3-Controller

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DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

f4pga / prjuray

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Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

fpga xilinx vivado fuzzer xilinx-fpga bitstream ultrascale symbiflow ultrascale-plus

Updated Feb 9, 2022
SystemVerilog

Parretto / DisplayPort

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DisplayPort IP-core

fpga xilinx lattice ip-core displayport

Updated Apr 25, 2025
SystemVerilog

ttchisholm / 10g-low-latency-ethernet

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10G Low Latency Ethernet

fpga xilinx ethernet systemverilog cocotb pyuvm

Updated Jul 15, 2023
SystemVerilog

tymonx / virtio

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Virtio implementation in SystemVerilog

cmake fpga model rtl verilog xilinx vivado systemverilog systemc hdl virtio verilator quartus

Updated Jan 23, 2018
SystemVerilog

esynr3z / axi_vip_demo

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Xilinx AXI VIP example of use

fpga xilinx systemverilog axi

Updated Apr 24, 2021
SystemVerilog

Luke7412 / IpLibrary

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Library containing various VHDL IPs

rtl ip xilinx vivado ip-xact systemverilog ipxact arty-a7 packaged-ip

Updated Jan 5, 2024
SystemVerilog

meiniKi / logIP

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Logic Analyzer IP Core

asic fpga digital amd ip verilog xilinx vivado ols systemverilog measurements hdl formal-verification basys3 hardware-description-language logicanalyzer sump logip symbiyosys

Updated Jul 23, 2022
SystemVerilog

dsa-shua / FPGA-SystolicArray

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Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis

Updated Feb 16, 2024
SystemVerilog

Kenta11 / simple_uart

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Simple UART modules in SystemVerilog

xilinx uart systemverilog

Updated Aug 10, 2023
SystemVerilog

pConst / xilinx_max_power

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Stress test power subsystem of your Xilinx FPGA board

development board fpga test power verilog xilinx systemverilog cooling soc shift-register digilent arty ultrascale zinq

Updated Apr 8, 2018
SystemVerilog

erwanregy / Neural-Network-on-an-FPGA

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Fully connected dense neural network in SystemVerilog, synthesisable to an FPGA for neural network computation acceleration

fpga neural-network rtl xilinx vivado zynq-7000

Updated Mar 15, 2023
SystemVerilog

SnrNotHere16 / Asynchronous-FIFO

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An FPGA implementation of Cummings' Asynchronous FIFO

Updated Apr 14, 2022
SystemVerilog

MasterPlayer / axis_uart_bridge

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FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

fpga zynq xilinx uart systemverilog artix uart-tx axi-stream uart-rx

Updated Dec 2, 2021
SystemVerilog

mankelly / VerilogProjects

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All projects that utilize the Verilog & SystemVerilog HDL's.

fpga embedded-systems verilog xilinx systemverilog system-on-chip

Updated Aug 23, 2022
SystemVerilog

ufukpalpas / Cellular-automata-game

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An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)

cellular-automata xilinx vivado systemverilog basys3 basys3-fpga

Updated Mar 20, 2020
SystemVerilog

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xilinx

Here are 27 public repositories matching this topic...

hdl-util / hdmi

trivialmips / nontrivial-mips

tymonx / logic

trivialmips / TrivialMIPS

BrianHGinc / BrianHG-DDR3-Controller

f4pga / prjuray

Parretto / DisplayPort

ttchisholm / 10g-low-latency-ethernet

tymonx / virtio

esynr3z / axi_vip_demo

Luke7412 / IpLibrary

meiniKi / logIP

dsa-shua / FPGA-SystolicArray

Kenta11 / simple_uart

pConst / xilinx_max_power

erwanregy / Neural-Network-on-an-FPGA

SnrNotHere16 / Asynchronous-FIFO

MasterPlayer / axis_uart_bridge

mankelly / VerilogProjects

ufukpalpas / Cellular-automata-game

Improve this page

Add this topic to your repo