[V1][TPU] Change kv cache shape.

[vanbasten23]

This PR changes the kv cache shape from [num_blocks, block_size, num_kv_heads, head_size] to [num_blocks, block_size, num_kv_heads * head_size], in accordance with the ragged paged attention kernel change pytorch/xla#8851, in order to unblock the multi-chip scenario:

• before the change, the ragged paged attention kernel will fail on some certain scenario ( eg if num_kv_head == 1 and dtype=bfloat16) because in this case num_kv_head is at the 2nd minor dimension and it will have implicit padding and waste memory. But if we change kv cache shape as in this PR, the num_kv_heads is no longer in 2nd minor dimension. For detail, please refer to the kernel change PR
• we can avoid key = key.view(num_tokens, self.num_kv_heads, self.head_size).

Test plan:

• VLLM_USE_V1=1 python vllm/examples/offline_inference/tpu.py 2>&1 | tee out.txt
• VLLM_USE_V1=1 pytest -s -v vllm/tests/entrypoints/llm/test_accuracy.py::test_lm_eval_accuracy_v1_engine 2>&1 | tee out.txt

cc @miladm @bythew3i

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[yaochengji]

LGTM, thanks!

[bythew3i]

Thanks Xiongfei!

[alexm-redhat]

Thanks @vanbasten23 !